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Prerequisites: CSE 2300W and ECE 3201; open only to students in the School of Engineering.
Grading Basis: Graded
Design of MOS transistors, including short channel effects in sub-micron devices; scaling laws; design rules. Layout of NMOS and CMOS logic gates; power-delay calculations. Design of static and/or dynamic memories. Laboratory emphasizes schematic capture, simulation, timing analysis and testing; layout of custom IC's; use of VHDL.
Last Refreshed: 16-SEP-19 05.20.32.275623 AM
|1203 3057 1 001||Spring 2020||Storrs||In Person||Wang, Lei||001||Reg||MoWe 11:15am‑12:05pm
|1203 3056 1 001L||Spring 2020||Storrs||In Person||Wang, Lei||001L||Reg||We 2:30pm‑4:30pm
|1203 9120 1 002L||Spring 2020||Storrs||In Person||Wang, Lei||002L||Reg||We 4:45pm‑6:45pm