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Prerequisites: CSE 2300W or 2301; ECE 3201; open only to students in the School of Engineering.
Grading Basis: Graded
Design of MOS transistors, including short channel effects in sub-micron devices; scaling laws; design rules. Layout of NMOS and CMOS logic gates; power-delay calculations. Design of static and/or dynamic memories. Laboratory emphasizes schematic capture, simulation, timing analysis and testing; layout of custom IC's; use of VHDL.
Last Refreshed: 16-APR-21 05.20.22.739451 AM
|1213 2990 1 001||Spring 2021||Storrs||In Person||Wang, Lei||001||Reg||MoWe 11:15am‑12:05pm
|1213 2989 1 001L||Spring 2021||Storrs||Distance Learning||Huang, Wenjie||001L||Reg||We 2:30pm‑4:30pm
||No Room Required - Online||12/12|
|1213 8345 1 002L||Spring 2021||Storrs||Distance Learning||Huang, Wenjie||002L||Reg||We 4:45pm‑6:45pm
||No Room Required - Online||14/15|