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3421. Very Large Scale Integrated (VLSI) Design and Simulation
4.00 credits
Prerequisites: CSE 2300W or 2301; ECE 3201; open only to students in the School of Engineering.
Grading Basis: Graded
Design of MOS transistors, including short channel effects in sub-micron devices; scaling laws; design rules. Layout of NMOS and CMOS logic gates; power-delay calculations. Design of static and/or dynamic memories. Laboratory emphasizes schematic capture, simulation, timing analysis and testing; layout of custom IC's; use of VHDL.
Last Refreshed: 16-APR-24 05.20.16.558219 AM
| Term | Campus | Instruction Mode | Instructor | Section | Session | Schedule | Location | Enrollment | Notes | |
|---|---|---|---|---|---|---|---|---|---|---|
| 1243 9673 1 001 | Spring 2024 | Storrs | In Person | Wang, Lei | 001 | Reg | MoWe 12:20pm‑1:10pm |
MCHU 202 | 36/30 | |
| 1243 9674 1 001L | Spring 2024 | Storrs | In Person | Li, Zongming | 001L | Reg | We 2:30pm‑4:30pm |
E2 307 | 18/15 | |
| 1243 9675 1 002L | Spring 2024 | Storrs | In Person | Li, Zongming | 002L | Reg | We 4:45pm‑6:45pm |
E2 307 | 18/15 |